| 전자부품 데이터시트 검색엔진 |
|
DLP4710AFQL 데이터시트(PDF) 33 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
DLP4710AFQL 데이터시트(HTML) 33 Page - Texas Instruments |
|
33 / 43 page ![]() 33 DLP4710 www.ti.com DLPS125 – NOVEMBER 2018 Product Folder Links: DLP4710 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 9.3 Power Supply Sequencing Requirements (1) Refer to Table 3 and Figure 23 for critical power-up sequence delay requirements. (2) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Recommended Operating Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down. Refer to Table 3 and Figure 23 for power-up delay requirements. (3) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in Recommended Operating Conditions. (4) When system power is interrupted, the DLPA3000/DLPA3005 initiates hardware power-down that disables VBIAS, VRESET and VOFFSET after the Micromirror Park Sequence. (5) Drawing is not to scale and details are omitted for clarity. Figure 22. Power Supply Sequencing Requirements (Power Up and Power Down) |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |