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DLP4710AFQL 데이터시트(PDF) 34 Page - Texas Instruments

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부품명 DLP4710AFQL
상세설명  0.47 1080p DMD
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DLP4710AFQL 데이터시트(HTML) 34 Page - Texas Instruments

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VOFFSET
VBIAS
VSS
VDD
VOFFSET
≤
< 6 V
VDD
VBIAS
≤
< 6 V
VSS
t
DELAY
20 V
16 V
12 V
8 V
4 V
0 V
12 V
8 V
4 V
0 V
34
DLP4710
DLPS125 – NOVEMBER 2018
www.ti.com
Product Folder Links: DLP4710
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Power Supply Sequencing Requirements (continued)
Table 3. Power-Up Sequence Delay Requirement
PARAMETER
MIN
MAX
UNIT
tDELAY
Delay requirement from VOFFSET power up to VBIAS power up
2
ms
VOFFSET
Supply voltage level at beginning of power–up sequence delay (see Figure 23)
6
V
VBIAS
Supply voltage level at end of power–up sequence delay (see Figure 23)
6
V
Refer to Table 3 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.
Figure 23. Power-Up Sequence Delay Requirement



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