CS42516 datasheet(55/90 Pages) CIRRUS

55 / 90 page

DS583F1

CS42516

6.9.2

AES FORMAT DETECTION (AES FORMATX)

Default = xxx

Function:

The CS42516 will auto-detect the AES format of the incoming S/PDIF stream and display the infor-

mation according to the following table.

6.9.3

SYSTEM CLOCK SELECTION (ACTIVE_CLK)

Default = x

0 - Output of PLL

1 - OMCK

Function:

This bit identifies the source of the internal system clock (MCLK).

6.9.4

RECEIVER CLOCK FREQUENCY (RCVR_CLKX)

Default = xxx

Function:

The CS42516 detects the ratio between the OMCK and the recovered clock from the PLL. Given the

absolute frequency of OMCK, this ratio may be used to determine the absolute frequency of the PLL

clock.

If a 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz clock is applied to OMCK and the OMCK_FREQX

bits are set accordingly (see “OMCK Frequency (OMCK Freqx)” on page 53), the absolute frequency

of the PLL clock is reflected in the RCVR_CLKX bits according to Table 14. If the absolute frequency

of the PLL clock does not match one of the frequencies given in Table 14, these bits will reflect the

closest available value.

If the frequency of OMCK is not equal to 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz, the contents

of the RCVR_CLKX bits will be inaccurate and should be disregarded. In this case, an external con-

troller may use the contents of the OMCK/PLL_CLK ratio register and the known OMCK frequency to

determine the absolute frequency of the PLL clock.

Note:

These bits are set to ‘111’b when the FRC_PLL_LK bit is ‘1’b.

AES

Format2

AES

Format1

AES

Format0

Description

Linear PCM

DTS®-CD

DTS®-LD

HDCD®

IEC 61937

Reserved

Table 13. AES Format Detection

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