| 전자부품 데이터시트 검색엔진 |
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STV0974 데이터시트(PDF) 8 Page - STMicroelectronics |
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STV0974 데이터시트(HTML) 8 Page - STMicroelectronics |
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8 / 69 page ![]() 8/61 STV0974 Functional description 4.1.2 Control Register map The STV0974 is controlled via a register map that is maintained by the STV0974 microprocessor. Each register in the map has an address and contains either read or read/write data. The read only registers detail the current state of the STV0974. Read/write registers can be written to in order to modify the default behavior of the STV0974. The map is accessed via I2C or via the microprocessor interface. Micro processor interface In microprocessor interface mode the STV0974 register map can be accessed by writing the address of the register to the port and then reading or writing the register value. Video output interface In streaming video mode, the STV0974 register map can be accessed via the I2C port on the STV0974. The STV0974 is addressed by supplying the device address, register address and value to be written or read. Microprocessor The microprocessor maintains the system interface via the register map. Any changes in system state are reflected in this map by the microprocessor and any changes commanded by the host system via this interface are then applied by the microprocessor. When the system is commanded to change state, the microprocessor configures the functional blocks from the STV0974 and the sensor into the requested mode. The register map is updated accordingly to reflect the new state of the hardware. The microprocessor monitors statistics gathered from the incoming image data and responds to changes in images. It adapts the functional block settings to correct for shifts in environmental conditions such as light level and illumination color temperature. The microcontroller will optimize these settings to provide the best quality image on all occasions. 4.1.3 Other functional blocks Power management The hardware state of the STV0974 can be controlled by the power down pin (PDN). Upon the application of power to the STV0974 and PDN release, the STV0974 power-on- reset cell issues a timed reset pulse and then releases the STV0974 into its boot state. The power-on-reset cell which output is the POR signal, is externally connected to the RST pin. Clocks In sleep mode, the STV0974 clock is derived from the clock signal applied to the CLK pin. In all other modes, the STV0974 clock is derived from the high speed clock received from the sensor. |
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