TUSB8044AI datasheet(12/63 Pages) TI1

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TUSB8044A

SLLSF92 – FEBRUARY 2019

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Electrical Characteristics (continued)

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

Applies to external inputs and bi-directional buffers

(2)

Applies to external outputs and bi-directional buffers

(3)

Applies to GRSTZ

(4)

Applies to pins with internal pullups/pulldowns.

(5)

Applies to external input buffers

IDD33_2H_

0SS_4HS

VDD33 current upstream port connected

to USB 2.0 Host, downstream port(s)

connected to 0 SS devices, and 4 HS

device.

VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;

IDD_2H_0S

S_4HS_BB

VDD current upstream port connected to

USB 2.0 Host, downstream port(s)

connected to 0 SS device, and 4 HS

device. Billboard enabled.

VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;

IDD33_2H_

0SS_4HS_

VDD33 current upstream port connected

to USB 2.0 Host, downstream port(s)

connected to 0 SS devices, and 4 HS

device. Billboard enabled.

VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;

3.3V I/O

VIH

High-level input voltage(1)

3.6

VIL

Low-level input voltage(1)

0.8

Input voltage

3.6

Output voltage(2)

3.6

Input transition time (tRISE and tFALL)

VHYS

Input hysteresis(3)

1.3 x

VDD33

VOH

High-level output voltage

IOH = -4 mA

2.4

VOL

Low-level output voltage

IOH = 4 mA

0.4

IOZ

High-impedance output current(2)

VI = 0 to VDD33;

-20

µA

IOZP

High-impedance output current with

internal pullup or pulldown resistor.(4)

VI = 0 to VDD33;

-250

250

µA

Input current(5)

VI = 0 to VDD33;

-15

µA

RPD

Internal pull-down resistance

13.5

27.5

kΩ

RPU

Internal pull-up resistance

14.5

kΩ

(1)

As long as GRSTz is de-asserted after both supplies are stable, there is no power-on relationship between VDD33 and VDD. If GRSTz is

only connected to a capacitor to GND, then VDD must be stable minimum of 10 µs before VDD33.

(2)

An active reset is required if the VDD33 supply is stable before VDD supply. This active reset shall meet the 3 ms power-up delay

counting from both power supplies stable to de-assertion of GRSTz.

(3)

MISC pins sampled at de-assertion of GRSTz: BATEN[4:1], AUTOENz, FULLPWRMGMTz, GANGED, SMBUSz, and PWRCTL_POL.

7.6 Timing Requirements

MIN

NOM

MAX

UNIT

Power-on timings. Refer to Figure 1

td1

VDD stable before VDD33 stable.

(1) (2)

td2

VDD and VDD33 before de-assertion of GRSTz.

tsu_io

Setup for MISC inputs. (3)

0.1

µs

thd_io

Hold for MISC inputs. (3)

0.1

µs

tVDD33_RAM

VDD33 supply ramp requirement.

0.2

100

tVDD_RAMP

VDD supply ramp requirement.

0.2

100

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