EPCQ32 datasheet(29/48 Pages) INTEL

29 / 48 page

Figure 5.

Write Non-Volatile Configuration Register Operation Timing Diagram

7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

nCS

DCLK

DATA0

DATA

Operation Code

(B1h)

High Impedance

Byte

LS Byte

MS Byte

NVCR In

1.7. Summary of Operation Codes

Table 31.

Summary of Operation Codes

Operation

Operation Code(14)

Address Bytes

Dummy Clock

Cycles

Data Bytes

DCLK fMAX

(MHz)

Read status register

05h

1 to infinite(15)

100

Read flag status register

70h

1 to infinite

100

Read bytes

03h

3 or 4

1 to infinite(15)

Read non-volatile

configuration register

B5h

100

Read device identification

9Fh

100

Fast read

0Bh

3 or 4

8(16)

1 to infinite(15)

100

Extended dual input fast

read

BBh

3 or 4

8(16)

1 to infinite(15)

100

Extended quad input fast

read

EBh

3 or 4

10(16)

1 to infinite(15)

100

Write enable

06h

100

Write disable

04h

100

Write status

01h

100

Write bytes

02h

3 or 4

1 to 256(17)

100

Write non-volatile

configuration register

B1h

100

continued...

(14) List MSB first and LSB last.

(15) The status register or data, is read out at least once and is continuously read out until the nCS

pin is driven high.

(16) You can configure the number of dummy clock cycles. Refer to Non-Volatile Configuration

(17) A write bytes operation requires at least one data byte. If more than 256 bytes are sent to the

device, only the last 256 bytes are written to the memory.

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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