Everest Semiconductor

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ES7210

Revision 11.1

4

March 2019

A master controller initiates the transmission by sending a “start” signal, which is defined as a

high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address.

It is a seven-bit chip address followed by a RW bit. The chip address must be 1000 0x, where x

equals AD1 AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge bit

is received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified

by the RW bit. The master can terminate the communication by generating a “stop” signal,

which is defined as a low-to-high transition at CDATA while CCLK is high.

instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you

must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the

register.

Chip Address

R/W

Register Address

Data to be written

start

1000 0 AD1 AD0

0

ACK

RAM

ACK

DATA

ACK

Stop

Chip Address

R/W

Register Address

Start

1000 0 AD1 AD0

0

ACK

RAM

ACK

Chip Address

R/W

Data to be read

Start

1000 0 AD1 AD0

1

ACK

Data

NACK

Stop

STOP

ACK

ACK

Write ACK

Chip Addr

START

bit 1 to 7

bit 1 to 8

Reg Addr

bit 1 to 8

Write Data

CCLK

CDATA

STOP

ACK

Write ACK

Chip Addr

START

bit 1 to 7

bit 1 to 8

Reg Addr

bit 1 to 8

Read Data

START

Read ACK

Chip Addr

bit 1 to 7

NO ACK

CCLK

CDATA