SYNPWM datasheet(10/57 Pages) FEELING

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FM8P73B

Web site: http://www.feeling-tech.com.tw

Rev1.0 Nov 20, 2013

P.10/FM8P73B

FEELING

TECHNOLOGY

2.1.3

STATUS (Status Register)

Address

Name

03h (r/w)

STATUS

̅̅̅̅

Legend: - = unimplemented, read as ‘0’.

This register contains the arithmetic status of the ALU, the RESET status.

If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these

three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO

̅̅̅̅ and PD

̅̅̅̅

bits are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be

different than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves

the STATUS Register as 000u u1uu (where u = unchanged).

C : Carry/borrow bit.

ADDAR

= 1, Carry occurred.

= 0, No Carry occurred.

SUBAR

= 1, No borrow occurred.

= 0, Borrow occurred.

Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR,

RLR) instructions, this bit is loaded with either the high or low order bit of the source register.

DC : Half carry/half borrow bit

ADDAR

= 1, Carry from the 4th low order bit of the result occurred.

= 0, No Carry from the 4th low order bit of the result occurred.

SUBAR

= 1, No Borrow from the 4th low order bit of the result occurred.

= 0, Borrow from the 4th low order bit of the result occurred.

Z : Zero bit.

= 1, The result of a logic operation is zero.

= 0, The result of a logic operation is not zero.

̅̅̅̅ : Power down flag bit.

= 1, after power-up or by the CLRWDT instruction.

= 0, by the SLEEP instruction.

̅̅̅̅ : Watch-dog timer overflow flag bit.

= 1, after power-up or by the CLRWDT or SLEEP instruction

= 0, a watch-dog time overflow occurred

PS : ROM Page Select bit

= 1, 200h ~ 2FFh

= 0, 000h ~ 0FFh

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