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Z86C34 데이터시트(PDF) 51 Page - Zilog, Inc.

부품명 Z86C34
상세설명  CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY
PDF  70 Pages
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제조업체  ZILOG [Zilog, Inc.]
홈페이지  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z86C34 데이터시트(HTML) 51 Page - Zilog, Inc.

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Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8® MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
51
Bit 2,1 are the Clock Source and Speed Select
When the BRG mode bit in the ASEXT register is set to 0,
these 3 bits, along with DR and PR in this register define
the ASCI baud rate. Bits 2, 1 and 0 specify a power-of-two
divider of the SCLK as defined in Table 22. These bits
should never be set to all 1s or erratic results may occur.
See the Baud Rate Generation Summary for more informa-
tion on setting the ASCI baud rate.
DR
Sampling Clock
0
Divide by 16
1
Divide by 64
Table 22. Clock Source and Speed Bits
SS2
SS1
SS0
Divider (DIV)
000
÷1
001
÷2
010
÷4
011
÷8
100
÷16
101
÷32
110
÷64
1
1
1
Reserved



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