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PIC12F635E/P 데이터시트(PDF) 56 Page - Microchip Technology

부품명 PIC12F635E/P
상세설명  8/14-PIN FLASH-BASED, 8-BIT CMOS MICROCONTROLLERS WITH NANOWATT TECHNOLOGY
PDF  196 Pages
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제조업체  MICROCHIP [Microchip Technology]
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PIC12F635/PIC16F636/639
DS41232B-page 54
Preliminary
© 2005 Microchip Technology Inc.
5.3
Using Timer0 with an External
Clock
When no prescaler is used, the external clock input is the
same as the prescaler output. The synchronization of
T0CKI, with the internal phase clocks, is accomplished
by sampling the prescaler output on the Q2 and Q4
cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 TOSC (and a
small RC delay of 20 ns) and low for at least 2 TOSC (and
a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
REGISTER 5-1:
OPTION_REG – OPTION REGISTER (ADDRESS: 81h)
Note:
The CMCON0 (19h) register must be ini-
tialized to configure an analog channel as
a digital input. Pins configured as analog
inputs will read ‘0’.
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RAPU: PORTA Pull-up Enable bit
1
= PORTA pull-ups are disabled
0
= PORTA pull-ups are enabled by individual values in the WPUDA register
bit 6
INTEDG: Interrupt Edge Select bit
1
= Interrupt on rising edge of RA2/T0CKI/INT/C1OUT pin
0
= Interrupt on falling edge of RA2/T0CKI/INT/C1OUT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1
= Transition on RA2/T0CKI/INT/C1OUT pin
0
= Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1
= Increment on high-to-low transition on RA2/T0CKI/INT/C1OUT pin
0
= Increment on low-to-high transition on RA2/T0CKI/INT/C1OUT pin
bit 3
PSA: Prescaler Assignment bit
1
= Prescaler is assigned to the WDT
0
= Prescaler is assigned to the Timer0 module
bit 2-0
PS<2:0>: Prescaler Rate Select bits
Note 1: A dedicated 16-bit WDT postscaler is available for the PIC12F635/PIC16F636/639.
See Section 12.11 “Watchdog Timer (WDT)” for more information.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value
TMR0 Rate WDT Rate(1)



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