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after the pin and connected through Rg to the sense point (see Fig. 17). The PCB traces connecting

these resistors to the reading point must be routed as parallel traces in order to avoid the pick-up of any

common mode noise. It's also important to avoid any offset in the measurement and to get a better pre-

cision, to connect the traces as close as possible to the sensing elements, dedicated current sense re-

connected to the PHASEx pin. DO NOT CONNECT THE PINS TOGETHER AND THEN TO THE HS

SOURCE! The device won't work properly because of the noise generated by the return of the high side

driver. In this case route two separate nets: connect the PHASEx pin to the HS Source (route together

with HGATEx) with a wide net (30 mils) and the ISENx pin to the LS Drain (route together with PGNDS).

Moreover, the PGNDS pin is always connected, through the Rg resistor, to the PGND: DO NOT CON-

NECT DIRECTLY TO THE PGND! In this case the device won't work properly. Route anyway to the LS

mosfet source (together with ISENx net).

Right and wrong connections are reported in Figure 18.

Symmetrical layout is also suggested to avoid any unbalance between the two phases of the converter.

Figure 18. PCB layout connections for sense nets.

EMBEDDING L6710-BASED VRMs…

When embedding the VRM into the application, additional care must be taken since the whole VRM is a

switching DC/DC regulator and the most common system in which it has to work is a digital system such

as MB or similar. In fact, latest MB has become faster and powerful: high speed data bus are more and

more common and switching-induced noise produced by the VRM can affect data integrity if not following

additional layout guidelines. Few easy points must be considered mainly when routing traces in which

switching high currents flow (switching high currents cause voltage spikes across the stray inductance of

the traces causing noise that can affect the near traces):

– When reproducing high current path on internal layers, please keep all layers the same size in order

to avoid "surrounding" effects that increases noise coupling.

– Keep safe guarding distance between high current switching VRM traces and data buses, especially

if high-speed data bus to minimize noise coupling.

– Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that must

walk near the VRD.

– Possible causes of noise can be located in the PHASE connections, Mosfet gate drive and Input volt-

age path (from input bulk capacitors and HS drain). Also PGND connections must be considered if

not insisting on a power ground plane. These connections, that can be possible sources of noise,

must be carefully kept far away from noise-sensitive data bus.

To LS Drain and Source

(or Sense Resistor)

To HS Gate and Source

(30 mils wide)

To HS Source

VIA to

GND Plane

NOT CORRECT

CORRECT