SC16C554DB datasheet(15/51 Pages) PHILIPS

15 / 51 page

9397 750 13133

Product data sheet

Rev. 01 — 9 February 2005

15 of 51

Philips Semiconductors

SC16C554B/554DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs

6.2 Internal registers

The SC16C554B/554DB provides 12 internal registers for monitoring and control. These

registers are shown in Table 5. These registers function as data holding registers

(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register

(FCR), line status and control registers (LCR/LSR), modem status and control registers

(MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user

accessible scratchpad register (SPR). Register functions are more fully described in the

following paragraphs.

[1]

These registers are accessible only when LCR[7] is a logic 0.

[2]

These registers are accessible only when LCR[7] is a logic 1.

6.3 FIFO operation

The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register

(FCR) bit 0. With SC16C554B devices, the user can set the receive trigger level, but not

the transmit trigger level. The receiver FIFO section includes a time-out function to ensure

data is delivered to the external CPU. An interrupt is generated whenever the Receive

Holding Register (RHR) has not been read following the loading of a character or the

receive trigger level has not been reached.

Table 5:

Internal registers decoding

Read mode

Write mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR) [1]

Receive Holding Register

Transmit Holding Register

Interrupt Enable Register

Interrupt Status Register

FIFO Control Register

Line Control Register

Modem Control Register

Line Status Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM) [2]

LSB of Divisor Latch

MSB of Divisor Latch

Table 6:

Flow control mechanism

Selected trigger level

(characters)

INT pin activation

Negate RTS

Assert RTS

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