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SC16C554DB 데이터시트(PDF) 30 Page - NXP Semiconductors

부품명 SC16C554DB
상세설명  5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
PDF  51 Pages
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제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SC16C554DB 데이터시트(HTML) 30 Page - NXP Semiconductors

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© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 9 February 2005
30 of 51
Philips Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 19:
Modem Control Register bits description
Bit
Symbol
Description
7:6
MCR[7:6]
Reserved; set to ‘0’.
5
MCR[5]
Autoflow control enable.
4
MCR[4]
Loop-back. Enable the local loop-back mode (diagnostics). In this mode
the transmitter output (TX) and the receiver input (RX), CTS, DSR, CD,
and RI are disconnected from the SC16C554B/554DB I/O pins. Internally
the modem data and control pins are connected into a loop-back data
configuration (see Figure 12). In this mode, the receiver and transmitter
interrupts remain fully operational. The Modem Control Interrupts are
also operational, but the interrupts’ sources are switched to the lower four
bits of the Modem Control. Interrupts continue to be controlled by the IER
register.
Logic 0 = Disable loop-back mode (normal default condition).
Logic 1 = Enable local loop-back mode (diagnostics).
3
MCR[3]
OP2, INTx enable. Used to control the modem CD signal in the loop-back
mode.
Logic 0 = Forces INTA to INTD outputs to the 3-state mode during the
16 mode (normal default condition). In the loop-back mode, sets OP2
(CD) internally to a logic 1.
Logic 1 = Forces the INTA to INTD outputs to the active mode during
the 16 mode. In the loop-back mode, sets OP2 (CD) internally to a
logic 0.
2
MCR[2]
OP1. This bit is used in the Loop-back mode only. In the loop-back mode,
this bit is used to write the state of the modem RI interface signal via
OP1.
1
MCR[1]
RTS
Logic 0 = Force RTS output to a logic 1 (normal default condition).
Logic 1 = Force RTS output to a logic 0.
Automatic RTS may be used for hardware flow control by enabling
MCR[5].
0
MCR[0]
DTR
Logic 0 = Force DTR output to a logic 1 (normal default condition).
Logic 1 = Force DTR output to a logic 0.



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