| 전자부품 데이터시트 검색엔진 |
|
GD25LB64CSIS 데이터시트(PDF) 18 Page - GigaDevice Semiconductor (Beijing) Inc. |
|
|
|||||||||||||||||||||||||||||
GD25LB64CSIS 데이터시트(HTML) 18 Page - GigaDevice Semiconductor (Beijing) Inc. |
|
18 / 70 page ![]() 1.8V Uniform Sector Dual and Quad Serial Flash GD25LB64C 18 7.2 Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program Security Registers and Reset commands. Figure2. Write Disable Sequence Diagram Command 0 1 2 3 4 5 6 7 04H CS# SCLK SI SO High-Z Figure2a. Write Disable Sequence Diagram (QPI) CS# SCLK IO0 IO1 IO2 IO3 0 1 Command 04H |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |