MT7697 datasheet(44/81 Pages) ETC2

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MT7697

Internet-of-Things Wireless Connectivity

Page 44 of 81

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

ADC IP (Analog)

AUXADC_MUX[3:0]

ADC_EN

1/2/4/8/16/32/64

average

Bus

interface

Memory

hclk_ck

MCU

Interrupt

4-to-1

MUX

ADC

Digital averaging

CLKOUT(2MS/s)

REG_AVG_MODE[2:0]

CLK(2MS/s)

Figure 2-17. Auxiliary ADC Block Diagram

2MHz Clock

Internal asyn. Clock

ADC sampling

ADC bit-cycling

ADC sampling

ADC bit-cycling

0.5 uS

ADC sampling

ADC bit-cycling

Sample #3

Sample #4

Sample #5

DOUT #1

DOUT #2

DOUT #3

AUXADC_DOUT

Figure 2-18. Auxiliary ADC Clock Timing Diagram

Auxiliary ADC Features:



Input channel number: 4 channels



Sampling and output data rate: 2MS/s



DNL without dithering and averaging: <±2LSB



DNL with dithering and averaging: <±1LSB



Dithering function: 16 levels with step size of 4LSB.

2.5.5

SPI Master Interface

MT7697 features one SPI master controller. It is used as an extension interface to control the

peripheral device on expansion port. The SPI master controller supports the clock rates of 0.25, 0.5, 1,

2, 4, 6, 8, 10, and 12MHz. It supports two options of clock polarity (CPOL) and two options of initial

clock phase (CPHA). SPI pins are multiplexed with I2S pins.

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