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GD25Q64CSJS 데이터시트(PDF) 22 Page - GigaDevice Semiconductor (Beijing) Inc.

부품명 GD25Q64CSJS
상세설명  3.3V Uniform Sector Dual and Quad Serial Flash
PDF  74 Pages
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제조업체  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q64C
22
7.10. Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3-
byte address (A23-
0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, and each bit is latched in on the
rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence
is shown in followed Figure11. The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out.
Dual I/O Fast Read with
“Continuous Read Mode”
The Dual I/O Fast Read command can further reduce
command overhead through setting the “Continuous Read Mode” bits
(M7-4) after the input 3-byte address (A23-A0).
If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Dual I/O
Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command
sequence is shown in followed Figure12.
If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command
requires the command code, thus returning to normal oper
ation. A “Continuous Read Mode” Reset command can be used
to reset (M5-4) before issuing normal command.
Figure 11. Dual I/O Fast Read Sequence Diagram (M5-4
≠ (1, 0))
Command
0
1
2
3
4
5
6
7
BBH
CS#
SCLK
SI(IO0)
SO(IO1)
8
9 10 11 12 13 14 15
6
4
2
0
6
4
2
0
16 17 18 19 20 21 22 23
6
4
2
0
6
4
7
5
3
1
7
5
3
1
7
5
3
1
7
5
A23-16
A15-8
A7-0
M7-4
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SI(IO0)
SO(IO1)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
SCLK
6
7
Byte1
Byte2
Byte3
Byte4
Dummy



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