GD25Q127CSFS datasheet(9/79 Pages) GIGADEVICE

9 / 79 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q127C

4. DEVICE OPERATION

SPI Mode

Standard SPI

The GD25Q127C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),

Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the

rising edge of SCLK and data shifts out on the falling edge of SCLK.

Dual SPI

The GD25Q127C supports Dual SPI operation when using the

“Dual Output Fast Read” and “Dual I/O Fast Read”

(3BH and BBH) commands. These commands allow data to be transferred to or from the device at twice the rate of the

standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.

Quad SPI

The GD25Q127C supports Quad SPI operation when using

the “Quad Output Fast Read”,” Quad I/O Fast Read”,

“Quad I/O Word Fast Read”(6BH,EBH,E7H)commands. These commands allow data to be transferred to or from the device

at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O

pins: IO0 and IO1, and WP# and HOLD#/RESET# pins become IO2 and IO3. Quad SPI commands require the non-volatile

Quad Enable bit(QE) in Status Register to be set.

Hold

The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware

pin for 8-pin packages. When HOLD/RST=0, the pin7 acts as HOLD#, the HOLD# function is only available when QE=0, If

QE=1, The HOLD# functions is disabled, the pin acts as dedicated data I/O pin.

The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write

status register, programming, or erasing in progress.

The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being

low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge

of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).

The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD

operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and

then CS# must be at low.

Figure1. Hold Condition

HOLD

CS#

SCLK

HOLD#

GD25Q127CSFS 데이터시트(PDF) 9 Page - GigaDevice Semiconductor (Beijing) Inc.