GD25Q127CSFS datasheet(14/79 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q127C

2. This feature is available on special order. (GD25Q127CxxSx)Please contact GigaDevice for details.

QE bit.

The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When

the QE bit is set to 0 (Default) the WP# pin and HOLD# / RESET# pin are enable. When the QE pin is set to 1, the Quad

IO2 and IO3 pins are enabled. (It is best to set the QE bit to 0 to avoid short issue if the WP# or HOLD# pin is tied directly

to the power supply or ground.)

LB3, LB2, LB1 bits.

The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the

write protect control and status to the Security Registers. The default state of LB3-LB1are 0, the security registers are

unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time

Programmable, once they are set to 1, the Security Registers will become read-only permanently.

CMP bit

The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the BP4-BP0

bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details.

The default setting is CMP=0.

SUS1, SUS2 bits

The SUS1 and SUS2 bits are read only bits in the status register (S15 and S10) that are set to 1 after executing an

Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the

SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command, software reset

(66H+99H) command as well as a power-down, power-up cycle.

DRV1, DRV0 bits

The DRV1&DRV0 bits are used to determine the output driver strength for the Read operations.

DRV1,DRV0

Driver Strength

100%

75%

50% (default)

25%

HOLD/RST bit

The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware

pin for 8-pin packages. When HOLD/RST=0, the pin acts as HOLD#, When the HOLD/RST=1, the pin acts as RESET#.

However, the HOLD# or RESET# function are only available when QE=0, If QE=1, The HOLD# and RESET# functions are

disabled, the pin acts as dedicated data I/O pin.

LPE bit

The Low Power Enable (LPE) bit is a non-volatile writable bit, indicating the status of Low Power Mode (LPM). When

LPE bit sets to 1, it means the device is in Low Power Mode, when LPE bit sets 0 (default), it means the device is not in

Low Power Mode.

GD25Q127CSFS 데이터시트(PDF) 14 Page - GigaDevice Semiconductor (Beijing) Inc.