AD9174 datasheet(65/164 Pages) AD

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Data Sheet

AD9174

Rev. A | Page 65 of 164

Complex Modulator Switch Configurations

The switch configurations described previously only support

complex samples with the NCO bypassed. To support complex

samples where the NCO is used, Configuration 3 can be

additionally reconfigured to operate on complex samples at the

output of the NCO(s), controlled by the EN_CMPLX_MOD bit

(Register 0x112, Bit 6). The specific configuration also depends

on whether NCO1 is enabled, as shown in Figure 85 and Figure 86.

To set up Configuration 3A, set the EN_CMPLX_MOD bit to 1

and set the switch to Configuration 3, with both NCO0 and

NCO1 enabled. The quadrature output of the NCO from each

main datapath is also routed to DAC1 (no longer sends zero

data out of DAC1 as in the default Configuration 3, shown in

Figure 84). If NCO1 is disabled and EN_CMPLX_MOD = 1,

the real output of NCO0 is sent to DAC0 and the quadrature

output of the NCO0 is set to DAC 1. This setup is similar to

Configuration 2, but with the samples picked up at the output of

NCO0 (see Figure 85 and Figure 86).

The divide by 2 block at the input of the mux switch can be

disabled using the CMPLX_MOD_DIV2_DISABLE bit in

6 dB lower than anticipated because the divide by 2 block is

enabled by default.

The complete list of SPI writes required to enable each

configuration is shown in Table 48.

÷2

NCO

DAC0 I DATA

÷2

SUM OF I NCO OUT DATA

TO DAC0 CORE

DAC0 Q DATA

NCO

DAC1 I DATA

SUM OF Q NCO OUT DATA

TO DAC1 CORE

DAC0 MOD SWITCH MODE

DAC1 MOD SWITCH MODE

DAC1 Q DATA

Figure 85. Configuration 3A, EN_CMPLX_MOD = 1, CMPLX_MOD_DIV2_DISABLE = 0, both Main NCOs Enabled—DAC0 = I0_NCO + I1_NCO, DAC1 = Q0_NCO +

Q1_NCO

NCO

DAC0 I DATA

DAC0 I NCO OUT DATA

TO DAC0 CORE

DAC0 Q DATA

NCO

DAC1 I DATA

DAC0 Q NCO OUT DATA

TO DAC1 CORE

DAC0 MOD SWITCH MODE

DAC1 MOD SWITCH MODE

DAC1 Q DATA

Figure 86. Configuration 3B, EN_CMPLX_MOD = 1, CMPLX_MOD_DIV2_DISABLE = 1, DAC 1 Main NCO Disabled—DAC0 = I0_NCO, DAC1 = Q0_NCO

Table 48. Required SPI Writes for Each Modulator Switch Configuration

Configuration

(EN_COMPLEX_MOD)

Bits[5:4] (DDSM_

MODE)

(Paged)

Bit 1 (CMPLX_MOD_

DIV2_DISABLE)

NCO0

Enable

NCO1

Enable

Configuration 0

Configuration 1

Configuration 2

Configuration 3

Complex Configuration 3A

Complex Configuration 3B

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