TMS320DM643 datasheet(67/160 Pages) TI

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5.3.4

Peripheral Power-Down Operation

5.3.5

Power-Down Modes Logic

PWRD

Internal Clock Tree

CPU

IFR

IER

CSR

PD1

PD2

Power-

Down

Logic

Clock

PLL

CLKIN

RESET

CLKOUT6

PD3

Internal

Peripherals

CLKOUT4

Clock

and Dividers

Distribution

TMS320DM643

A. External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic.

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

Eight larger caps (4 for each supply) can be placed further away for bulk decoupling. Large bulk caps (on

the order of 100 µF) should be furthest away (but still as close as possible). No less than 4 large caps per

supply (8 total) should be placed outside of the BGA.

Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of

any component, verification of capacitor availability over the product’s production lifetime should be

considered.

The DM643 device can be powered down in three ways:

• Power-down due to pin configuration

• Power-down due to software configuration – relates to the default state of the peripheral configuration

bits in the PERCFG register.

• Power-down during run-time via software configuration

On the DM643 device, the HPI and EMAC and MDIO peripherals are controlled (selected) at the pin level

during chip reset (e.g., HD5 and MAC_EN pins).

The McASP0, McBSP0, VP1, VP2, and I2C0 peripheral functions are selected via the peripheral

configuration (PERCFG) register bits.

For more detailed information on the peripheral configuration pins and the PERCFG register bits, see the

Device Configurations section of this document.

Figure 5-6 shows the power-down mode logic on the DM643.

Figure 5-6. Power-Down Mode Logic(A)

DM643 Peripheral Information and Electrical Specifications

TMS320DM643 데이터시트(PDF) 67 Page - Texas Instruments

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