TMS320DM643 datasheet(69/160 Pages) TI

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5.3.7

C64x Power-Down Mode with an Emulator

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

Table 5-2. Characteristics of the Power-Down Modes

PRWD Field

POWER-DOWN

WAKE-UP METHOD

EFFECT ON CHIP'S OPERATION

(BITS 15–10)

MODE

000000

No power-down

—

001001

PD1

Wake by an enabled interrupt

CPU halted (except for the interrupt logic)

Power-down mode blocks the internal clock inputs at the

boundary of the CPU, preventing most of the CPU's logic from

Wake by an enabled or

010001

PD1

switching. During PD1, EDMA transactions can proceed be-

non-enabled interrupt

tween peripherals and internal memory.

Output clock from PLL is halted, stopping the internal clock

structure from switching and resulting in the entire chip being

011010

PD2(1)

Wake by a device reset

halted. All register and internal RAM contents are preserved. All

functional I/O "freeze" in the last state when the PLL clock is

turned off.

Input clock to the PLL stops generating clocks. All register and

internal RAM contents are preserved. All functional I/O "freeze"

in the last state when the PLL clock is turned off. Following

reset, the PLL needs time to re-lock, just as it does following

011100

PD3(1)

Wake by a device reset

power-up.

Wake-up from PD3 takes longer than wake-up from PD2

because the PLL needs to be re-locked, just as it does following

power-up.

All others

Reserved

—

(1)

When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in

nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these

conditions, peripherals will not operate according to specifications.

If user power-down modes are programmed, and an emulator is attached, the modes will be masked to

allow the emulator access to the system. This condition prevails until the emulator is reset or the cable is

removed from the header. If power measurements are to be performed when in a power-down mode, the

emulator cable should be removed.

When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution

command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will

fail. A DSP reset will be required to get the DSP out of PD2/PD3.

DM643 Peripheral Information and Electrical Specifications

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