DAC5687IPZP datasheet(24/72 Pages) TI

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DAC5687

SLWS164B – FEBRUARY 2005 – REVISED JUNE 2005

Name

Address

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

(MSB)

Bit 0

DAC_TEST

0x1C

0x00

factory use only

phstr_clkdiv_sel

factory use only

0x1D

0x00

factory use only

0x1E

0x00

factory use only

0x1F

0x00

BIT 7

BIT 0

sleep_daca

sleep_dacb

hpla

hplb

unused

version(2:0)

sleep_daca: DAC A sleeps when set, operational when cleared.

sleep_dacb: DAC B sleeps when set, operational when cleared.

hpla:

A side first FIR filter in high-pass mode when set, low-pass mode when cleared.

hplb:

B side first FIR filter in high-pass mode when set, low-pass mode when cleared.

version(2:0): A hardwired register that contains the version of the chip. Read Only.

BIT 7

BIT 0

pll_div(1:0)

pll_freq

pll_kv

interp(1:0)

inv_plllock

fifo_bypass

pll_div(1:0): PLL VCO divider; {00 = 1, 01 = 2, 10 = 4, 11 = 8}.

pll_freq:

PLL VCO center frequency; {0 = low center frequency, 1 = high center frequency}.

pll_kv:

PLL VCO gain; {0 = high gain, 1 = low gain}.

interp(1:0): FIR Interpolation; {00 = X2, 01 = X4, 10 = X4L, 11 = X8}. X4 uses lower power than x4L, but f

DAC =

320 MHz max when NCO or QMC are used.

inv_plllock: Multi-function bit depending on clock mode.

fifo_bypass: When set, the internal 4-sample FIFO is disabled. When cleared, the FIFO is enabled.

Table 2. inv_plllock Bit Modes

PLLVDD

dual_clk

inv_pllock

fifo_bypass

DESCRIPTION

0 V

Input data latched on PLLLOCK pin rising edges, FIFO disabled.

0 V

Input data latched on PLLLOCK pin falling edges, FIFO dis-

abled.

0 V

Input data latched on PLLLOCK pin rising edges, FIFO enabled

and must be sync’d.

0 V

Input data latched on PLLLOCK pin falling edges, FIFO enabled

and must be sync’d.

0 V

Input data latched on CLK1/CLK1C differential input. Timing

between CLK1 and CLK2 rising edges must be tightly controlled

(500 ps max at 500-MHz CLK2). PLLLOCK output signal is

always low. The FIFO is always disabled in this mode.

0 V

Input data latched on CLK1/CLK1C differential input. No phase

relationship required between CLK1 and CLK2. The FIFO is

employed to manage the internal handoff between the CLK1

input clock and the CLK2 derived output clock; the FIFO must

be sync’d. The PLLLOCK output signal reflects the internally

generated FIFO output clock.

0 V

Not a valid setting. Do not use.

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