SLAC Products
27
Therefore, during this multiplexing, the CD1 bit always
has loop-detect status and the CD1B bit always has
ground-key detect status.
T h i s
multiple xin g
state
c hanges
a l most
instantaneously within the QSLAC device but the SLIC
device may require a slightly longer time period to
respond to this detect state change before its DET
output settles and becomes valid. To accommodate
this delay difference, the internal signals within the
QSLAC device are isolated by 15.625
µs before
allowing any change to the CD1 bit and CD1B bit
latches. This operation is further described by the E1
multiplex timing diagram in Figure 9. In this timing
diagram, the E1 signal represents the actual signal
presented to the E1 output pin. The GK Enable pulse
allows CD1 pin data to be routed through the CD1B
latch. The LD Enable pulse allows CD1 pin data to be
routed through the CD1 latch. The uncertain states of
the SLIC’s DET output, and the masked times where
that DET data is ignored are shown in this timing
diagram. Using this isolation of masked times, the CD1
and CD1B registers are guaranteed to contain
accurate representations of the SLIC detector output.
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