HB28K032MM3 datasheet(49/91 Pages) RENESAS

49 / 91 page

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3

Rev.0.02, Sep.15.2004, page 49 of 89

The host command and the card response are clocked out with the rising edge of the host clock. The delay

between host command and card response is N

CR clock cycles.

The following timing diagram is relevant

for host command CMD3:

S T

content

CRC E Z

* * * * * *

CMD

Host command

S T

content

CRC E Z Z Z

Response

NCR cycles

Host active

Card active

Command Response Timing (Identification Mode)

There is just one Z bit period followed by P bits pushed up by the responding card. The following timing

diagram is relevant for all host commands followed by a response, except CMD1, CMD2 and CMD3:

S T

content

CRC E Z Z P

* * *

CMD

Host command

S T

content

CRC E Z Z Z

Response

Card active

NCR cycles

Host active

Command Response Timing (Data Transfer Mode)

• Card identification and card operation conditions timing

The card identification (CMD2) and card operation condition (CMD1) timing are processed in the open-

drain mode. The card response to the host command starts after exactly N

ID clock cycles.

S T

content

CRC E Z

* * *

CMD

Host command

S T

content

Z Z Z

CID or OCR

NID cycles

Host active

Card active

Identification Timing (Card Identification Mode)

• Last card response - next host command timing

After receiving the last card response, the host can start the next command transmission after at least N

clock cycles. This timing is relevant for any host command.

S T

content

CRC E Z

* * * * * *

CMD

Response

S T

content

CRC E

Host command

NRC cycles

Card active

Host active

Timing Response End to Next CMD Start (Data Transfer Mode)

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