STA450A datasheet(25/66 Pages) STMICROELECTRONICS

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STA450A

Invert_sclk

Bit 2

0: LRCLK and PCM_OUT sampled on the falling edge of the SCLK

1: LRCLK and PCM_OUT sampled on the raising edge of the SCLK

Format

Bit 3

0: the output is in I2S format.

1: the output is in SONY format.

Invert_lrclk

Bit 4

0: LRCLK = 0 (low) will select the left channel.

1: LRCLK = 1 (high) will select the left channel

Pcm_dif

Bit 5

0: data are in the last SCLK cycles of LRCLK (right aligned)

1: data are in the first SCLK cycles of LRCLK (left aligned)

Pcm_ord

Bit 6

0: the transmission is done LSB first.

1: the transmission is done MSB first.

Pcm_iec_chansel

Bit 7

0: no iec958 output.

1: iec958 output, data on I2S pin (PCSD) are no more valid.

HOST_APLL48_LSB

Address

: 0x50

Type

: R/W

Software Reset

: NA

Hardware Reset

: NA

HOST_APLL48_MSB

Address

: 0x51

Type

: R/W

Software Reset

: NA

Hardware Reset

: NA

Description

The HOST_APLL48_LSB and the HOST_APLL48_MSB are considered logically concatenated and

contain the fractional values for the Audio Fractional PLL for the Fs = 48KHz family.

The registers have to be programmed before the start_up of the DSP.

HOST_APLL48_XDIV

Address

: 0x52

7654

3210

7654

3210

7654

3210

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