SSD1306 datasheet(40/65 Pages) ETC2

40 / 65 page

Solomon Systech

Apr 2008 P 40/59

Rev 1.1

SSD1306

10.1.16 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h)

This command consists of two functions:

• Display Clock Divide Ratio (D)(A[3:0])

Set the divide ratio to generate DCLK (Display Clock) from CLK. The divide ratio is from 1 to 16,

with reset value = 1. Please refer to section 8.3 for the details relationship of DCLK and CLK.

• Oscillator Frequency (A[7:4])

Program the oscillator frequency Fosc that is the source of CLK if CLS pin is pulled high. The 4-bit

value results in 16 different frequency settings available as shown below. The default setting is

1000b.

10.1.17 Set Pre-charge Period (D9h)

This command is used to set the duration of the pre-charge period. The interval is counted in number of

DCLK, where RESET equals 2 DCLKs.

10.1.18 Set COM Pins Hardware Configuration (DAh)

This command sets the COM signals pin configuration to match the OLED panel hardware layout. The table

below shows the COM pin configuration under different conditions (for MUX ratio =64):

Table 10-3 : COM Pins Hardware Configuration

Conditions

COM pins Configurations

1 Sequential COM pin configuration (DAh A[4] =0)

COM output Scan direction: from COM0 to COM63 (C0h)

Disable COM Left/Right remap (DAh A[5] =0)

2 Sequential COM pin configuration (DAh A[4] =0)

COM output Scan direction: from COM0 to COM63 (C0h)

Enable COM Left/Right remap (DAh A[5] =1)

128 x 64

ROW32

ROW63

ROW0

ROW31

Pad 1,2,3,…->126

Gold Bumps face up

SSD1306Z

COM0

COM63

COM32

128x 64

ROW0

ROW31

ROW32

ROW63

Pad 1,2,3,…->126

Gold Bumps face up

SSD1306Z

COM0

COM31

COM32

COM63

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