Rev. 1.0 / Nov. 2013

8

RESET

Input

Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when

RESET is HIGH. RESET must be HIGH during normal operation.

1.20V for DC high and 0.30V for DC low.

DQ

Input /

Output

Data Input/ Output: Bi-directional data bus.

DQU, DQL,

DQS, DQS,

DQSU, DQSU,

DQSL, DQSL

Input /

Output

Data Strobe: output with read data, input with write data. Edge-aligned with read data,

centered in write data. The data strobe DQS, DQSL, and DQSU are paired with differential

signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the

system during reads and writes. DDR3 SDRAM supports differential data strobe only and

does not support single-ended.

TDQS, TDQS

Output

Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via

Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance

function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11

= 0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4

DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.

NC

No Connect: No internal electrical connection is present.

NF

No Function

Supply DQ Power Supply: 1.35 V +0.100/- 0.067 V

Supply DQ Ground

Supply Power Supply: 1.35 V +0.100/- 0.067 V

Supply Ground

Supply Reference voltage for DQ

Supply Reference voltage for CA

ZQ

Supply Reference Pin for ZQ calibration

Note:

Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination.

Symbol

Type

Function