STM32L4A6XG datasheet(40/282 Pages) STMICROELECTRONICS

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Functional overview

STM32L4A6xG

40/282

DS11584 Rev 8

3.13

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be

achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

3.14

Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features

implementation.

Direct memory access (DMA) is used in order to provide high-speed data transfer between

peripherals and memory as well as memory to memory. Data can be quickly moved by DMA

without any CPU actions. This keeps CPU resources free for other operations.

The two DMA controllers have 14 channels in total, each dedicated to managing memory

access requests from one or more peripherals. Each has an arbiter for handling the priority

between DMA requests.

The DMA supports:

•

14 independently configurable channels (requests)

•

Each channel is connected to dedicated hardware DMA requests, software trigger is

also supported on each channel. This configuration is done by software.

•

Priorities between requests from channels of one DMA are software programmable (4

levels consisting of very high, high, medium, low) or hardware in case of equality

(request 1 has priority over request 2, etc.)

•

Independent source and destination transfer size (byte, half word, word), emulating

packing and unpacking. Source/destination addresses must be aligned on the data

size.

•

Support for circular buffer management

•

3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)

logically ORed together in a single interrupt request for each channel

•

Memory-to-memory transfer

•

Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral

transfers

•

Access to Flash, SRAM, APB and AHB peripherals as source and destination

•

Programmable number of data to be transferred: up to 65536.

Table 7. DMA implementation

DMA features

DMA1

DMA2

Number of regular channels

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