LS1020A datasheet(33/71 Pages) FREESCALE

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Architecture

TWR-LS1021A Reference Manual, Rev. 0

2-18

Freescale Semiconductor

2.13

2D ACE - Display Controller Port

The LS1021A has an internal Display Control Unit (2D ACE), suitable for driving video at resolutions

up to XVGA (1024 x 768 x 24 bpp x 60 Hz); higher resolutions such as UXGA may be possible depending

on overall system memory bandwidth. The display buffer resides in main memory, with the R-G-B pixel

data streaming out at a rate sufficient to maintain the LCD raster. Since the DCU handles all the raster

generation, all that remains is to convert the data stream into a format suitable for the LCD displays.

The DCU hardware signals are extracted from the QE_TDM port and then drives either DVI or HDMI

ports onboard as in the below Figure 2-13.

Figure 2-13. DIU architecture

NOTE

The DIU is an output-only port, so multiple levels of multiplexing and

translation do not effect the output, as long as good signal integrity is

maintained.

2.13.1

Display Control Unit (2D-ACE) programming/setup information

The DCU needs to be programmed to generate the pixel data/clock/enables in order to properly drive the

selected encoder. Specific encoder information follows, but for all three the following steps apply:

•

Program the DCU with the following information:

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