 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
LS1022A 데이터시트(PDF) 23 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
LS1022A 데이터시트(HTML) 23 Page - Freescale Semiconductor, Inc |
|
|
23 / 71 page  Architecture TWR-LS1021A Reference Manual, Rev. 0 2-8 Freescale Semiconductor Figure 2-6. Clock architecture 2.6.1 SYSCLK / DDRCLK SYSCLK and DDRCLK are provided by an IDT 6V49205BNLGI, a programmable frequency synthesizer with hardware presets. The device is strapped to provide 100 MHz to SYSCLK and 67 MHz to DDRCLK during power up. LS1021A requires 64 MHz to 100 MHz for both SYSCLK and DDRCLK. Spread Spectrum Clocking (SSC) options are supported for SYSCLK and DDRCLK by SMBUS. Because SSC reduces the clock rate, reducing the performance somewhat, it is not a preferred operating mode. Table 2-4. SYSCLK frequency options FS[0:1] SYSCLK Notes 0 0 66.67 MHz n/a 0 1 80 MHz n/a 1 0 100.00 MHz default 1 1 83.33 MHz n/a Table 2-5. DDRCLK frequency options DDRCLK pin DDRCLK Notes pull-up 66.67 MHz n/a pull-down 100.00 MHz Default on TWR-LS1021A |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
