TDC-GPX2 datasheet(21/77 Pages) AMSCO

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ams Datasheet

Page 21

[v1-03] 2017-Dec-18

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TDC- GP X2 − Register Description

Configuration Register Overview

The configuration registers are organized in 17 addresses of one byte. All configuration registers are accessible via

the SPI interface. They can be read and written individually or with an incremental access. For monitoring the chip

it is possible to observe at the PARITY pin whether the sum of all set bits is even or odd.

Figure 23:

Configuration Register Overview

Addr

<D7>

<D6>

<D5>

<D4>

<D3>

<D2>

<D1>

<D0>

PIN_ENA_RSTIDX

PIN_ENA_DISABLE

PIN_ENA_LVDS_OUT

PIN_ENA_REFCLK

PIN_ENA_STOP4

PIN_ENA_STOP3

PIN_ENA_STOP2

PIN_ENA_STOP1

HIGH_RESOLUTION

CHANNEL_COMBINE

HIT_ENA_STOP4

HIT_ENA_STOP3

HIT_ENA_STOP2

HIT_ENA_STOP1

BLOCKWISE_

FIFO_READ

COMMON_FIFO_

READ

LVS_DOUBLE_DATA_

RATE

STOP_DATA_BITWIDTH

REF_INDEX_BITWIDTH

REFCLK_DIVISIONS (Lower byte)

REFCLK_DIVISIONS (Middle byte)

Fixed value*: (0000b)

REFCLK_DIVISIONS (Upper bits)

Fixed value*: (110b)

LVDS_ TEST_

PATTERN

Fixed value*: (0000b)

REFCLK_BY _

XOSC

Fixed value*: (1b)

LVDS_DATA_VALID_ ADJUST

Fixed Value*: (0011b)

Fixed value*: (10100001b)

Fixed value*: (00010011b)

Fixed value*: (00000000b)

Fixed value*: (00001010b)

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