EM78P451SWM datasheet(19/54 Pages) EMC

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EM78P451S

8-Bit Microcontroller with OTP ROM

Product Specification (V1.0) 06.01.2004

• 15

(This specification is subject to change without further notice)

The watchdog timer is a free running on-chip RC oscillator. The WDT will keep

running even when the oscillator driver has been turned off (i.e. in sleep mode).

During normal operation or sleep mode, a WDT time-out (if enabled) will cause the

device to reset. The WDT can be enabled or disabled any time during the normal

mode by software programming (if Code Option bit ENWDT is "1"). Refer to

WDTEbit of IOCE register. Without presacler, the WDT time-out period is

approximately 18 ms1.

4.4 I/O Ports

The I/O registers, from Port 5 to Port 9, are bi-directional tri-state I/O ports. P60~P67,

P74~P75, and P90~P91 provide internal pull-high. P60~P67, P74~P75, and P90~P95

provide programmable wake-up function through software. P76~P77 can have

open-drain output by software control. P80~P81 are the R-option pins which are

enabled by software. When the R-option function is used, it is recommended that P80

and P81 are used as output pins. During R-option enabled state, P80 and P81 must be

programmed as input pins. If an external resistor is connected to P80 (P81) for the

R-option function, the current consumption should be taken as an important factor in

the applications for low power consideration.

The I/O ports can be defined as "input" or "output" pins by the I/O control registers

(IOC5~IOC9) under program control. The I/O registers and I/O control registers are

both readable and writable. The I/O interface circuit is shown in Fig. 7. Note that the

reading path source of input and output pins is different when reading the I/O port.

CLK(=Fosc/2)

Data Bus

SYNC

2cycles

TCC(R1)

PAB

TCC overflow interrupt

WDT

WDTE

(in IOCE)

WDT timeout

8-bit Counter

8- to -1 MUX

PSR0~PSR2

MUX

PAB

Fig. 6 Block Diagram of TCC WDT

1 NOTE: Vdd = 5V, set up time period = 16.2ms ± 30%

Vdd = 3V, set up time period = 18.0ms ± 30%

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