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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SAF-C161PI 데이터시트(PDF) 39 Page - Infineon Technologies AG |
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SAF-C161PI 데이터시트(HTML) 39 Page - Infineon Technologies AG |
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39 / 400 page  &3, 0HPRU\ 2UJDQL]DWLRQ User’s Manual 3-3 1999-08 3.1 Internal ROM Area The C161PI may reserve an address area of variable size (depending on the version) for on-chip mask-programmable ROM/Flash/OTP memory (organized as X * 32). The lower 32 KByte of this on-chip memory block are referred to as “Internal ROM Area”. Internal ROM accesses are globally enabled or disabled via bit ROMEN in register SYSCON. This bit is set during reset according to the level on pin EA, or may be altered via software. If enabled, the internal ROM area occupies the lower 32 KByte of either segment 0 or segment 1 (alternate ROM area). This mapping is controlled by bit ROMS1 in register SYSCON. Note: The size of the internal ROM area is independent of the size of the actual implemented Program Memory. Also devices with less than 32 KByte of Program Memory or with no Program Memory at all will have this 32 KByte area occupied, if the Program Memory is enabled. Devices with a larger Program Memory provide the mapping option only for the internal ROM area. Devices with a Program Memory size above 32 KByte expand the ROM area from the middle of segment 1, i.e. starting at address 01’8000 H. The internal Program Memory can be used for both code (instructions) and data (constants, tables, etc.) storage. Code fetches are always made on even byte addresses. The highest possible code storage location in the internal Program Memory is either xx’xxFE H for single word instructions, or xx’xxFC H for double word instructions. The respective location must contain a branch instruction (unconditional), because sequential boundary crossing from internal Program Memory to external memory is not supported and causes erroneous results. Any word and byte data read accesses may use the indirect or long 16-bit addressing modes. There is no short addressing mode for internal ROM operands. Any word data access is made to an even byte address. The highest possible word data storage location in the internal Program Memory is xx’xxFE H. For PEC data transfers the internal Program Memory can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers. The internal Program Memory is not provided for single bit storage, and therefore it is not bit addressable. Note: The ‘x’ in the locations above depend on the available Program Memory and on the mapping. The internal Program Memory may be enabled, disabled or mapped into segment 0 or segment 1 under software control. Chapter “System Programming” shows how to do this and reminds of the precautions that must be taken in order to prevent the system from crashing. |
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