전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

SAF-C161PI 데이터시트(PDF) 49 Page - Infineon Technologies AG

부품명 SAF-C161PI
상세설명  16-Bit Single-Chip Microcontroller
PDF  400 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  INFINEON [Infineon Technologies AG]
홈페이지  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

SAF-C161PI 데이터시트(HTML) 49 Page - Infineon Technologies AG

Back Button SAF-C161PI Datasheet HTML 45Page - Infineon Technologies AG SAF-C161PI Datasheet HTML 46Page - Infineon Technologies AG SAF-C161PI Datasheet HTML 47Page - Infineon Technologies AG SAF-C161PI Datasheet HTML 48Page - Infineon Technologies AG SAF-C161PI Datasheet HTML 49Page - Infineon Technologies AG SAF-C161PI Datasheet HTML 50Page - Infineon Technologies AG SAF-C161PI Datasheet HTML 51Page - Infineon Technologies AG SAF-C161PI Datasheet HTML 52Page - Infineon Technologies AG SAF-C161PI Datasheet HTML 53Page - Infineon Technologies AG Next Button
Zoom Inzoom in Zoom Outzoom out
 49 / 400 page
background image
&3,
7KH &HQWUDO 3URFHVVLQJ 8QLW &38
User’s Manual
4-1
1999-08
4
The Central Processing Unit (CPU)
Basic tasks of the CPU are to fetch and decode instructions, to supply operands for the
arithmetic and logic unit (ALU), to perform operations on these operands in the ALU, and
to store the previously calculated results. As the CPU is the main engine of the C161PI
controller, it is also affected by certain actions of the peripheral subsystem.
Since a four stage pipeline is implemented in the C161PI, up to four instructions can be
processed in parallel. Most instructions of the C161PI are executed in one machine cycle
(2 CPU clock periods) due to this parallelism.
This chapter describes how the pipeline works for sequential and branch instructions in
general, and which hardware provisions have been made to speed the execution of jump
instructions in particular. The general instruction timing is described including standard
and exceptional timing.
While internal memory accesses are normally performed by the CPU itself, external
peripheral or memory accesses are performed by a particular on-chip External Bus
Controller (EBC), which is automatically invoked by the CPU whenever a code or data
address refers to the external address space.
Figure 4-1
CPU Block Diagram



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com