CS5342

DS608PP2

19

4.7

Synchronization of Multiple Devices

In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure

synchronous sampling, the MCLK and LRCK must be the same for all of the CS5342’s in the system.

4.8

Capacitor Size on the Reference Pin (FILT+)

The CS5342 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this decou-

pling capacitor will affect the low frequency distortion performance as shown in Figure 22, with larger capacitor val-

ues used to optimize low frequency distortion performance. The THD+N curves in Figure 22 were measured with

VA = VD = VL = 5 V in Single-Speed Master Mode using a 1 kHz input tone of magnitude -1 dB Full-Scale.

Figure 22. CS5342 THD+N versus Frequency

47 uF

100 uF

22 uF

10 uF

6.8 uF

4.7 uF

3.3 uF

2.2 uF

1 uF

5.6 uF