CS5342

22

DS608PP2

7.

REVISION HISTORY

Release

Date

Changes

A1

April 2003

-Initial Advance Release.

A2

July 2003

-Modify serial port timing specs.

-Add Applications section on speed mode detect.

PP1

August 2004

-Change 2700 pF capacitors to 2200 pF in analog input buffer diagram.

-Update Output Sample Range table.

-Add new Applications section about capacitor on FILT+ pin.

-Correct Max MCLK period under “Switching Characteristics.”

-Replace MCLK low/high timing specifications with duty cycle specification.

-Redefine slave mode timing specifications under “Switching Characteristics.”

-Add requirement of SCLK/LRCK = 48x in Double and Quad Speed Modes.

-Increase minimum VL specification from 1.7 V to 2.38 V.

-Specify VA and VD at 5 V,

±5% for Quad-Speed Slave Mode.

-Reduce gain error specification under Analog Characteristics.

-Improve minimum and maximum specifications for full-scale input voltage.

-Initial Preliminary Release.

PP2

Aug 2004

Update to include lead-free device ordering information.

Table 5. Revision History