Advanced Clock Drivers Devices

4

Freescale Semiconductor

MPC92433

Table 2. Function Table

Control

1. Default states are set by internal input pull-up or pull-down resistors of 75 k

Ω.

01

Inputs

REF_SEL

1

Selects REF_CLK input as PLL reference clock

Selects the XTAL interface as PLL reference

clock

M[9:0]

PLL feedback divider (10-bit) parallel programming interface

NA[2:0]

010

PLL post-divider parallel programming interface. See Table 9

NB

0

PLL post-divider parallel programming interface. See Table 9

P

1

PLL pre-divider parallel programming interface. See Table 8

PLOAD

0

Selects the parallel programming interface. The

internal PLL divider settings (M, NA, NB and P) are

equal to the setting of the hardware pins. Leaving the

M, NA, NB and P pins open (floating) results in a

application/programming section.

The internal PLL divider settings (M, NA, NB and

P) are set and read through the serial interface.

ADR[1:0]

00

Address bit = 0

Address bit = 1

SDA, SCL

See Programming the MPC92433

BYPASS

1

PLL function bypassed

PLL function enabled

TEST_EN

0

Application mode. Test mode disabled.

Factory test mode is enabled

CLK_STOPx

1

Output Qx is disabled in logic low state. Synchronous

disable is only guaranteed if NB = 0.

Output Qx is synchronously enabled

MR

The device is reset. The output frequency is zero and

the outputs are asynchronously forced to logic low

state.

After releasing reset (upon the rising edge of MR and

independent on the state of PLOAD), the MPC92433

reads the parallel interface (M, NA, NB and P) to

acquire a valid startup frequency configuration. See

application/programming section.

The PLL attempts to lock to the reference signal.

Outputs

LOCK

PLL is not locked

PLL is frequency locked