DMOS Microstepping Driver with Translator

A3979

7

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Figure 1. Logic Interface Timing Diagram

Table 1. Microstep Resolution Truth Table

MS1

MS2

Microstep Resolution

Excitation Mode

L

L

Full Step

2 Phase

H

L

Half Step

1-2 Phase

L

H

Quarter Step

W1-2 Phase

H

H

Sixteenth Step

4W1-2 Phase

Timing Requirements

A

B

C

D

50%

STEP

MS1/MS2/

DIR/RESET

Dwg. WP-042

SLEEP

E

A. Minimum Command Active Time

Before Step Pulse (Data Set-Up Time) ..... 200 ns

B. Minimum Command Active Time

After Step Pulse (Data Hold Time) ............ 200 ns

C. Minimum STEP Pulse Width ...................... 1.0

μs

D. Minimum STEP Low Time ......................... 1.0

μs

E. Maximum Wake-Up Time ......................... 1.0 ms