PCF2127TSLASH2Y datasheet(82/100 Pages) PHILIPS

82 / 100 page

PCF2127

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 19 December 2014

82 of 100

NXP Semiconductors

PCF2127

Accurate RTC with integrated quartz crystal for industrial applications

14.2 I2C-bus timing characteristics

[1]

A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to

bridge the undefined region of the falling edge of SCL.

[2]

Cb is the total capacitance of one bus line in pF.

[3]

The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, tf is 250 ns. This allows

series protection resistors to be connected between the SDA/CE pin, the SCL pin, and the SDA/SCL bus lines without exceeding the

maximum tf.

[4]

tVD;ACK is the time of the acknowledgement signal from SCL LOW to SDA (out) LOW.

[5]

tVD;DAT is the minimum time for valid SDA (out) data following SCL LOW.

[6]

Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.

Table 93.

I2C-bus characteristics

All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 %

and 70 % with an input voltage swing of VSS to VDD (see Figure 56).

Symbol

Parameter

Standard mode

Fast-mode (Fm)

Unit

Min

Max

Min

Max

Pin SCL

fSCL

SCL clock frequency

100

400

kHz

tLOW

LOW period of the SCL clock

4.7

1.3

s

tHIGH

HIGH period of the SCL clock

4.0

0.6

s

Pin SDA/CE

tSU;DAT

data set-up time

250

100

tHD;DAT

data hold time

Pins SCL and SDA/CE

tBUF

bus free time between a STOP

and START condition

4.7

1.3

s

tSU;STO

set-up time for STOP condition

4.0

0.6

s

tHD;STA

hold time (repeated) START

condition

4.0

0.6

s

tSU;STA

set-up time for a repeated START

condition

4.7

0.6

s

rise time of both SDA and SCL

signals

[1][2][3] -

1000

20 + 0.1Cb

300

fall time of both SDA and SCL

signals

[1][2][3] -

300

20 + 0.1Cb

300

tVD;ACK

data valid acknowledge time

[4] 0.1

3.45

0.1

0.9

s

tVD;DAT

data valid time

[5] 300

tSP

pulse width of spikes that must be

suppressed by the input filter

[6] -50

-50

PCF2127T/2Y 데이터시트(PDF) 82 Page - NXP Semiconductors

PCF2127T/2Y 데이터시트(HTML) 82 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

데이터시트 다운로드

링크 URL