82845GL datasheet(4/193 Pages) INTEL

4 / 193 page

Intel® 82845G/82845GL/82845GV GMCH

Datasheet

3.5.1

DRAM Controller/Host-Hub Interface Device Registers (Device 0) .. 48

3.5.1.1

VID—Vendor Identification Register (Device 0) ................ 50

3.5.1.2

DID—Device Identification Register (Device 0)................. 50

3.5.1.3

PCICMD—PCI Command Register (Device 0) ................. 51

3.5.1.4

PCISTS—PCI Status Register (Device 0)......................... 52

3.5.1.5

RID—Revision Identification Register (Device 0).............. 53

3.5.1.6

SUBC—Sub-Class Code Register (Device 0)................... 53

3.5.1.7

BCC—Base Class Code Register (Device 0).................... 53

3.5.1.8

MLT—Master Latency Timer Register (Device 0) ............. 54

3.5.1.9

HDR—Header Type Register (Device 0) .......................... 54

3.5.1.10 APBASE—Aperture Base Configuration Register

(Device 0)............................................................................. 55

3.5.1.11 SVID—Subsystem Vendor Identification Register

(Device 0)............................................................................. 56

3.5.1.12 SID—Subsystem Identification Register (Device 0) .......... 56

3.5.1.13 CAPPTR—Capabilities Pointer Register (Device 0) ......... 56

3.5.1.14 AGPM—AGP Miscellaneous Configuration Register

(Device 0)............................................................................. 57

3.5.1.15 GC—Graphics Control Register (Device 0)....................... 58

3.5.1.16 DRB[0:3]—DRAM Row Boundary Register (Device 0) ..... 60

3.5.1.17 DRA—DRAM Row Attribute Register (Device 0) .............. 61

3.5.1.18 DRT—DRAM Timing Register (Device 0) ......................... 62

3.5.1.19 DRC—DRAM Controller Mode Register (Device 0) .......... 63

3.5.1.20 PAM[0:6]—Programmable Attribute Map Registers

(Device 0)............................................................................. 64

3.5.1.21 FDHC—Fixed SDRAM Hole Control Register (Device 0) . 67

3.5.1.22 SMRAM—System Management RAM Control Register

(Device 0)............................................................................. 67

3.5.1.23 ESMRAMC—Extended System Management RAM Control

3.5.1.24 ACAPID—AGP Capability Identifier Register (Device 0) .. 69

3.5.1.25 AGPSTAT—AGP Status Register (Device 0) ................... 69

3.5.1.26 AGPCMD—AGP Command Register (Device 0) .............. 70

3.5.1.27 AGPCTRL—AGP Control Register (Device 0).................. 70

3.5.1.28 APSIZE—Aperture Size Register (Device 0) .................... 71

3.5.1.29 ATTBASE—Aperture Translation Table Register

Device 0).............................................................................. 71

3.5.1.30 AMTT—AGP MTT Control Register (Device 0)................. 72

3.5.1.31 LPTT—AGP Low Priority Transaction Timer Register

(Device 0)............................................................................. 72

3.5.1.32 GMCHCFG—GMCH Configuration Register (Device 0) ... 73

3.5.1.33 ERRSTS—Error Status Register (Device 0) ..................... 74

3.5.1.34 ERRCMD—Error Command Register (Device 0).............. 75

3.5.1.35 SMICMD—SMI Command Register (Device 0) ................ 76

3.5.1.36 SCICMD—SCI Command Register (Device 0) ................. 76

3.5.1.37 SKPD—Scratchpad Data Register (Device 0) .................. 76

3.5.1.38 CAPREG—Capability Identification Register (Device 0)... 77

3.5.2

Host-to-AGP Bridge Registers (Device 1)......................................... 78

3.5.2.1

VID1—Vendor Identification Register (Device 1) .............. 79

3.5.2.2

DID1—Device Identification Register (Device 1)............... 79

3.5.2.3

PCICMD1—PCI Command Register (Device 1) ............... 80

3.5.2.4

PCISTS1—PCI Status Register (Device 1)....................... 81

3.5.2.5

RID1—Revision Identification Register (Device 1)............ 82

3.5.2.6

SUBC1—Sub-Class Code Register (Device 1)................. 82

3.5.2.7

BCC1—Base Class Code Register (Device 1).................. 82

3.5.2.8

MLT1—Master Latency Timer Register (Device 1) ........... 83

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