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RM0016 데이터시트(PDF) 132 Page - STMicroelectronics |
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RM0016 데이터시트(HTML) 132 Page - STMicroelectronics |
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132 / 467 page ![]() Window watchdog (WWDG) RM0016 132/467 DocID14587 Rev 14 15.6 Hardware watchdog option If hardware watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WWDG_CR register is not used. Refer to the option byte description in the datasheet. 15.7 Using Halt mode with the WWDG (WWDGHALT option) The following recommendation applies if Halt mode is used when the watchdog is enabled. Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WWDG reset immediately after waking up the microcontroller. 15.8 WWDG interrupts None. 15.9 WWDG registers 15.9.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x7F 7 654 3210 WDGA T6 T5 T4 T3 T2 T1 T0 rs rw rw rw rw rw rw rw Bit 7 WDGA: Activation bit(1) This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every 12288 fCPU cycles (approximately). A reset is produced when it rolls over from 0x40 to 0x3F (T6 becomes cleared). 1. This bit is not used if the hardware watchdog option is enabled by option byte. |
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