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RF3000
Rev A4 031216
IEEE802.11b DSSS Receive Summary
1. Drive RXPE High.
2. RF3000 looks for incoming valid Barker Code.
3. RF3000 sets ACQ bit in Register 0x01.
4. When the Start Frame Delimiter is identified, the RF3000 sets the SFD bit in Register 0x01.
5. RF3000 Extracts Header information.
This information is copied into the RF3000 RX Status, Service fields and presented on the RXDATA Pin with Clocks on
DATA CLK.
6. This will be followed by 16 bit times of no clock transitions.
7. RF3000 Drives RXRDY high, and clocks Received Data on the rising edge of DATA CLK.
8. RF3000 Drives RXRDY low at the end of the data packet.
The RF3000 has provision for an alternate Receive Data port interface. In the receiver interface, the DATACLK is
inverted, and an extra clock is asserted after RXRDY goes 'low' indicating the end of the received packet, see Figure
13a. The alternate Transmit interface is enabled by writing 0x08 into RF3000 Register 0x1C.
RXRDY
Preamble and
Header
Extraction
Rate Determined from Received IEEE802.11 Signal Field
Data
RXPE
Header
Data
RXDATA
DATACLK
32CLK
Cycles
Figure 13. IEEE802.11b Receive Timing Overview
RXRDY
Preamble and
Header
Extraction
Rate Determined from Received IEEE802.11 Signal Field
Data
RXPE
Header
Data
RXDATA
DATACLK
32CLK
Cycles
Figure 13a. Alternate Receiver Interface
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