11-326
RF3000
Rev A4 031216
Pin
Function
Description
Interface Schematic
1
TXPE
Input from the external network processor. The rising edge of TX PE
places the transmitter into an active state. The falling edge of TX PE
indicates the end of transmission.
2RXPE
When active (value '1'), the receiver is powered up and CCA circuitry is
active.
3MCLK
Master clock. This should be a 44MHz for IEEE802.11b and is used to
generate other internally used clocks.
4TXRDY
Indicates that the chip is ready to accept data from the MAC for Tx.
5RXRDY
Indicates that the chip is ready to deliver data to the MAC from Rx.
6VDDD
Output from 2.2V internal voltage regulator for digital sections of
RF3000. This pin should not be connected to anything.
7GNDD
Ground signal for digital power.
8
CCA
Clear channel assessment per IEEE802.11b standard. “1” indicates
“clear”.
9LNAGS
LNA gain select. “1” indicates “high gain”.
10
TXDATA
TX data stream input.
11
DATACLK
Data clock for TX and RX data.
12
RXDATA
RX data stream output.
13
CSb
In SPI mode this pin serves as serial port chip select.
14
CCLK
Serial port clock. This clock is used for SPI mode.
15
CDIN
In SPI mode this pin serves as CDIN input.
16
CDOUT
In SPI mode this pin serves as CDOUT output.
17
RXVGC
Analog receive variable gain control output: 1.2V to 2.0V.
18
NC
Not connected.
19
IIN
Analog I input.
20
QIN
Analog Q input.
21
VDDA
DC power for analog sections 3.3V.
22
GNDA
Ground signal for analog power.
23
IOUT
Analog I output: 1.6V to 1.8V.
24
QOUT
Analog Q output: 1.6V to 1.8V.
25
TXVGC
Analog voltage for transmitter variable gain control: 1.2V to 2.0V.
26
ANTSEL
Antenna selection signal for diversity receiver.
27
RESET
Pin='1' chip reset.
Pin='0' standard operation.
28
VREF
Reference voltage for internal data converters.
Connect to RF2948 VREF or set to 1.7VDC.
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
