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TLE75620-EST 데이터시트(PDF) 35 Page - Infineon Technologies AG |
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TLE75620-EST 데이터시트(HTML) 35 Page - Infineon Technologies AG |
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35 / 81 page ![]() Datasheet 35 Rev. 1.0 2017-11-23 TLE75620-EST SPIDER+ 12V Power Stages Figure 17, Figure 18 show a concept drawing of the implementation. Nevertheless, the maximum allowed load inductance is limited. The clamping structure protects the device in all operative modes (Sleep, Idle, Active, Limp Home). Figure 17 Output Clamp concept Figure 18 Output Clamp concept PowerStage_XS.emf Auto -configurable Channel (as high -side) VS L, RL VOUTn_S IL_S L, RL IL_D VOUT_S(CL) VDS(CL) I L IL OUTn_D OUTn_S VDS GND Auto-configurable Channel (as low-side) VOUT_S(CL) VDS(CL) OUTn_D OUTn_S VDS GND PowerStage_HS.emf High-side Channel VS L, R L VOUTn IL_S VOUT(CL) VDS(CL) IL VSn OUTn VDS GND |
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