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ADC3541 데이터시트(PDF) 35 Page - Texas Instruments |
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ADC3541 데이터시트(HTML) 35 Page - Texas Instruments |
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35 / 68 page ![]() FCLK D12 D11 FCLK D11 2-Wire 8x Serialization 1-Wire 16x Serialization DCLK DCLK A 1 <15:0> A 0 <15:0> A 0 D13 A 0 D11 A 0 D9 A 0 D7 A 0 D5 A 0 D3 A 0 D1 A 0 D12 A 0 D10 A 0 D8 A 0 D6 A 0 D4 A 0 D2 A 0 D0 A 1 D13 A 1 D11 A 1 D9 A 1 D7 A 1 D5 A 1 D3 A 1 D12 A 1 D10 A 1 D8 A 1 D6 A 1 D4 A 1 D2 A 1 D1 A 1 D0 A 0 D15 A 0 D14 A 1 D15 A 1 D14 Figure 7-35. Output Data Format in Real Decimation Table 7-7 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK frequencies based on output resolution (R), number of serial CMOS lanes (L) and real decimation setting (M). Furthermore the table shows an actual lane rate example for the 2- and 1-wire interface, 16-bit output resolution and real decimation by 16. Table 7-7. Serial CMOS Lane Rate Examples with Real Decimation and 16-bit Output Resolution DECIMATION SETTING ADC SAMPLING RATE OUTPUT RESOLUTION # of WIRES FCLK DCLKIN, DCLK DOUT M FS R L FS / M / 2 (L = 2) FS / M (L = 1) [DOUT] / 2 FS x R / L / M 16 65 MSPS 16 2 2.03125 MHz 16.25 MHz 32.5 MHz 1 4.0625 MHz 32.5 MHz 65 MHz www.ti.com ADC3541 SBAS840 – JULY 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: ADC3541 |
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