VSC7440 datasheet(294/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

277

U = R / (R + 2S × 256)

3.27.6.3 Setting Up Frame Rate

The following table lists the frame rate configuration registers.

To define a minimum frame spacing, set

DSM::TX_RATE_LIMIT_MODE.TX_RATE_LIMIT_FRAME_RATE_ENA to 1.

At start of payload, a counter is loaded with the value stored in

DSM::TX_FRAME_RATE_START_CFG.TX_FRAME_RATE_START.

What is counted as payload is defined by DSM::TX_RATE_LIMIT_MODE.PAYLOAD_PREAM_CFG and

DSM::TX_RATE_LIMIT_MODE.PAYLOAD_CFG.

With every payload byte transmitted, the counter is decremented by 1.

At end of frame, the GAP will be extended by the counter value, if above 12.

3.27.7

Error Detection

The following table lists the error detection status registers.

If one or both of BUF_OFLW_STICKY and BUF_UFLW_STICKY sticky bits are set, the port module was

set up erroneously.

TX_RATE_LIMIT_STICKY is set when an IPG of a frame is increased due to one of the three rate limiting

modes.

3.28

Layer 1 Timing

There are eight recovered clocks, four outputs that provide timing sources for external timing circuitry in

redundant timing implementations, and four internal clocks for the timing-recovery circuit. The following

tables list the registers and pins associated with Layer 1 timing.

Table 204 •

Rate Limiting Frame Rate Registers Overview

Target::Register.Field

Description

Replication

DSM::TX_RATE_LIMIT_MODE.

TX_RATE_LIMIT_FRAME_RATE_ENA

Enables txRateLimitFrameRate mode.

Per port

DSM::TX_FRAME_RATE_START_CFG.

TX_FRAME_RATE_START

Frame rate start.

Per port

Table 205 •

Error Detection Status Registers Overview

Target::Register.Field

Description

Replication

DSM::BUF_OFLW_STICKY.BUF_OFLW_STICKY Cell buffer had an overflow.

Per port

DSM::BUF_UFLW_STICKY.BUF_UFLW_STICKY Cell buffer had an underrun.

Per port

DSM::TX_RATE_LIMIT_STICKY.TX_

RATE_LIMIT_STICKY

IPG was increased by one of the three rate limiting

modes.

Per port.

Table 206 •

Layer 1 Timing Configuration Registers

Description

HSIO::SYNC_ETH_CFG

Configures recovered clocks. Replicated per recovered clock.

HSIO::SYNC_ETH_PLL_CFG

Additional PLL recovered clock configuration. Replicated per

recovered clock.

HSIO::SYNC_ETH_SD10G_CFG

Additional 10G recovered clock configurations. Replicated per 10G

interface.

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