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VSC7440 데이터시트(PDF) 53 Page - Microsemi Corporation

부품명 VSC7440
상세설명  L2/L3 Enterprise Gigabit Ethernet Switch with 10 Gbps Links
PDF  444 Pages
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제조업체  MICROSEMI [Microsemi Corporation]
홈페이지  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7440 데이터시트(HTML) 53 Page - Microsemi Corporation

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Functional Descriptions
VMDS-10492 VSC7440 Datasheet Revision 4.2
36
Important The EPG is intended for use with laboratory or in-system testing equipment only. Do not use
the EPG testing feature when the PHY is connected to a live network.
To use the EPG feature, set PHY_1000BT_EPG2.EPG_ENA to 1.
When PHY_1000BT_EPG2.EPG_RUN_ENA is set to 1, the PHY begins transmitting Ethernet packets
based on the settings in the PHY_1000BT_EPG1 and PHY_1000BT_EPG2 registers. These registers
set:
•
Source and destination addresses for each packet
•
Packet size
•
Inter-packet gap
•
FCS state
•
Transmit duration
•
Payload pattern
If PHY_1000BT_EPG1.TRANSMIT_DURATION_CFG is set to 0, PHY_1000BT_EPG1.EPG_RUN_ENA
is cleared automatically after 30,000,000 packets are transmitted.
3.8.7.2
CRC Counters
Two separate CRC counters are available in the PHY: a 14-bit good CRC counter available through
PHY_CRC_GOOD_CNT.CRC_GOOD_PKT_CNT and a separate 8-bit bad CRC counter in
PHY_CTRL_EXT4.CRC_1000BT_CNT.
3.8.7.3
Far-End Loopback
The far-end loopback testing feature is enabled by setting
PHY_CTRL_EXT1.FAR_END_LOOPBACK_ENA to 1. When enabled, it forces incoming data from a link
partner on the current media interface, into the MAC interface of the PHY, to be re-transmitted back to the
link partner on the media interface as shown in the following illustration. The incoming data also appears
on the receive data pins of the MAC interface. Data present on the transmit data pins of the MAC
interface is ignored when using this testing feature.
Figure 15 •
Far-End Loopback Diagram
3.8.7.4
Near-End Loopback
When the near-end loopback testing feature is enabled (by setting PHY_CTRL.LOOPBACK_ENA to 1),
data on the transmit data pins (TXD) is looped back in the PCS block, onto the device receive data pins
(RXD), as shown in the following illustration. When using this testing feature, no data is transmitted over
the network.
Figure 16 •
Near-End Loopback Diagram
Link Partner
PHY
Rx
Tx
Switch
Cat5
Link Partner
PHY
Rx
Tx
Switch
Cat5



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