VSC7440 datasheet(414/444 Pages) MICROSEMI

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Electrical Specifications

VMDS-10492 VSC7440 Datasheet Revision 4.2

397

Figure 147 •

Test Circuit for Recovered Clock Output Signals

The following table lists the AC specifications for the recovered clock outputs.

6.2.15

Two-Wire Serial Interface

This section provides the AC specifications for the two-wire serial interface signals TWI_SCL and

TWI_SDA. The two-wire serial interface signals are GPIO alternate functions. For more information

about the GPIO pin mapping, see GPIO Overlaid Functions, page 352.

The two-wire serial interface signals are compatible with the Philips I2C-BUS specifications, except for

the minimum rise time and fall time requirements for fast mode.

Figure 148 •

Two-Wire Serial Read Timing Diagram

Table 316 •

Recovered Clock Output AC Specifications

Parameter

Symbol Minimum

Maximum

Unit Condition

RCVRD_CLK[3:0] clock frequency

161.33

MHz

Clock duty cycle

Measured at 50% threshold.

RCVRD_CLK[3:0] rise time and fall time

tR, tF

1.5

Squelching delay from SGMII signal to

RCVRD_CLK[3:0]

200

Squelch enabled.

RCVRD_CLK[3:0] peak-to-peak jitter,

bandwidth between 12 kHz and 10 MHz1,

60 second gate time

Maximum jitter on the recovered signal.

200

Jitter-free input to SerDes Rx.

RCVRD_CLK[3:0] peak-to-peak jitter,

bandwidth between 10 MHz and

80 MHz1, 60 second gate time

200

Jitter-free input to SerDes Rx.

Device Under Test

Signal Measurement Point

8 pF

tHIGH

tLOW

tSU_DAT

tHD_STA

tSU_STO

tBUF

tHD_DAT

tSU_STA

tHD_STA

TWI_SDA

TWI_SCL

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