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H5GQ2H24AFR-R0C 데이터시트(PDF) 94 Page - Hynix Semiconductor

부품명 H5GQ2H24AFR-R0C
상세설명  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
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제조업체  HYNIX [Hynix Semiconductor]
홈페이지  http://www.skhynix.com/kor/main.do
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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
94
H5GQ2H24AFR
Figure 59. Non-Gapless READs
DBI
DBI
n+7
n
Bank a,
Col m
Col m
CL = CLmrs = 6
T8
T10
T11
T0
T1
T3
T6
T6n
T7
T7n
T10n
T9
T9n
DONʹT CARE
TRANSITIONING DATA
DO
DO
DBI
DBI
m+7
m+7
m
m
DO
DO
n+7
n
Bank b,
Col n
Col n
tCCD
CL = CLmrs = 6
2.  WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes.  WCK2CK training determines the needed offset between WCK and CK.
4.  tCCD = tCCDL when bank groups are enabled and both READs access banks in the same bank group; otherwise tCCD=tCCDS. 
5.  Before the READ commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
1.  CLmrs = 6 is shown as an example.  Actual supported values will be found in the MR and AC timings sections.
3.  EDC may be on or off.  See Figure 58 for EDC Timing.
Notes:
6.  tWCK2DQI = 0 is shown for illustration purposes.
NOP
READ
READ
NOP
NOP
NOP
NOP
NOP
NOP
CK
CK#
COMMAND
DQ
DBI#
WCK#
WCK
ADDRESS
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