전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

H5GQ2H24AFR-R0C 데이터시트(PDF) 96 Page - Hynix Semiconductor

부품명 H5GQ2H24AFR-R0C
상세설명  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  HYNIX [Hynix Semiconductor]
홈페이지  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C 데이터시트(HTML) 96 Page - Hynix Semiconductor

Back Button H5GQ2H24AFR-R0C Datasheet HTML 92Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 93Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 94Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 95Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 96Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 97Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 98Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 99Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 100Page - Hynix Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 96 / 172 page
background image
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
96
H5GQ2H24AFR
Figure 61. READ to WRITE
DBI
DBI
n+7
n
DO
DO
n+7
n
DO
DO
DBI
DBI
m+7
m+7
m
m
WL = WLmrs = 3
CL = CLmrs = 6
Bank a,
Col m
Col m
T9
T11
T12
T0
T1
T6
T7
T7n
T8
T6n
T10
T10n
DONʹT CARE
TRANSITIONING DATA
Bank b,
Col n
Col n
tRTW
T11n
2.  WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes.  WCK2CK training determines the needed offset between WCK and CK.
respectively must be met.
1.  WLmrs = 3 and CLmrs = 6 is shown as an example.  Actual supported values will be found in the MR and AC timings sections.
3.  EDC may be on or off.  See Figure 58 for EDC Timing.
5.  For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins. 
6.  Before the READ and WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD or tRCDWR
4.  tWTR = tWTRL when bank groups is enabled and both WRITE and READ access banks in the same bank group, otherwise tWTR=tWTRS.
Notes:
7.  tWCK2DQI, tWCKDQO = 0 is shown for illustration purposes.
NOP
READ
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
CK
CK#
COMMAND
ADDRESS
DQ
DBI#
WCK#
WCK
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com